hanbit hm d4m32m2ve url:www.hbe.co.kr h anbit electronics co.,ltd. rev.1.0 (august.2002) 1 general description the HMD4M32M2VE is a 4m x 32 bit dynamic ram high - density memory module. the module consists of two cmos 4m x 16 bit drams in 50 - pin tsop packages mounted on a 72 - pin. a 0.1 or 0.22uf decoupling capacitor is mounted on the pri nted circuit board for each dram components. the module is a single in - line memory module with edge connections and is intended for mounting in to 72 - pin edge connector sockets. all module components may be powered from a single 3.3v dc power supply. all i nputs and outputs are lv ttl - compatible. features w part identification HMD4M32M2VE ---- lead finish solder HMD4M32M2VEg - lead finish gold w access times : 50, 60ns w high - density 16mbyte design w 4k cycles/64ms ref, gold w singl e +3.3v 0.3v power supply w jedec standard pinout w edo mode operation w lv ttl compatible inputs and outputs w fr4 - pcb design option s marking w timing 50ns access - 5 60 n s access - 6 w packages 72 - pin simm m performance range speed trac tcac trc 5 50ns 13ns 84ns 6 60ns 15ns 104ns pin names pin name function pin name function pin name function a0 - a11 address input(4k ref) /ras0 row address strobe vss ground dq0 - dq31 data in/out /cas0 - /cas3 column address strobe nc no connection /w read/write input pd1 - pd4 presence detect vcc power(+3.3v) 16mbyte(4mx32) d ram simm edo mode, 4k refresh, 3.3v part no. hm d4m32m2ve, hmd 4m32m2veg pin assignment pin symbol pin symbol pin symbol pin symbol 1 vss 19 a10 37 nc 55 dq11 2 dq0 20 dq4 38 nc 56 dq27 3 dq16 21 dq20 39 vss 57 dq12 4 dq1 22 dq5 40 /cas0 58 dq28 5 dq17 23 dq21 41 /cas2 59 vcc 6 dq2 24 dq6 42 /cas3 60 dq29 7 dq18 25 dq22 43 /cas1 61 dq13 8 dq3 26 dq7 44 /ras0 62 dq30 9 dq19 27 dq23 45 nc 63 dq14 10 vcc 28 a7 46 nc 64 dq31 11 nc 29 a11 47 /w 65 dq15 12 a0 30 vcc 48 nc 66 nc 13 a1 31 a8 49 dq8 67 pd1 14 a2 32 a9 50 dq24 68 pd2 15 a3 33 nc 51 dq9 69 pd3 16 a4 34 nc 52 dq25 70 pd4 17 a5 35 nc 53 dq10 71 nc 18 a6 36 nc 54 dq26 72 vss
hanbit hm d4m32m2ve url:www.hbe.co.kr h anbit electronics co.,ltd. rev.1.0 (august.2002) 2 functional block dia gram toall drams 0.1uf or 0.22uf capacitor for each dram dq0 - dq7 dq8 - dq15 dq16 - dq23 dq24 - dq31 /ras0 /cas0 /cas1 /cas2 /cas3 /w a0 - a11 /ras /lcas /ucas /oe /w a0 - a11 u0 /ras /lcas /ucas /oe /w a0 - a11 u2 vcc vss dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15
hanbit hm d4m32m2ve url:www.hbe.co.kr h anbit electronics co.,ltd. rev.1.0 (august.2002) 3 absolute maximum rat ings parameter symbol rating voltage on any pin relative to vss v in ,out - 0.5v to 6.5v voltage on vcc supply relative to vss vcc - 0.5v to 4.6v power dissipation p d 2w storage temperature t stg - 55 o c to 150 o c short circuit output current i os 50ma w permanent device damage may occur if " absolute maximum ratings" ar e exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc o perating conditions ( voltage reference to v ss , t a =0 to 70 o c ) parameter symbol min typ . max unit supply voltage vcc 3.0 3.3 3.6 v ground vss 0 0 0 v input high voltage v ih 2.0 - +5.5 v input low voltage v il - 0.3 - 0.8 v dc and operating cha racte ristics symbol speed min max units - 5 - 220 ma i cc1 - 6 - 200 ma i cc2 - 4 ma - 5 - 220 ma i cc3 - 6 - 200 ma - 5 - 220 ma i cc4 - 6 - 200 ma i cc5 - 600 ma - 5 - 220 ma i cc6 - 6 - 200 ma i l(l) - 10 10 m a i o(l) - 10 10 m a v oh 2.4 - v v ol - 0.4 v i cc1 : operating current * (/ras , /cas , address cycling @t rc =min.) i cc2 : standby current ( /ras=/cas=v ih )
hanbit hm d4m32m2ve url:www.hbe.co.kr h anbit electronics co.,ltd. rev.1.0 (august.2002) 4 i cc3 : /ras only refresh current * (/cas=v ih , /ras, address cycling @t rc =min ) i cc4 : fast page mode current * (/ras=v il , /cas, address cycling @t pc =min ) i cc5 : standby current (/ras=/cas=vcc - 0.2v ) i cc6 : /cas - before - /ras refresh current * (/ras and /cas cycling @t rc =min ) * note: i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address cad be changed maximum once while /ras=v il . in i cc4 , address can be changed maximum once within one page mode cycle. capacitance ( t a =25 o c, vcc = 3.3v, f = 1mz ) description symbol min max units input capacitance (a0 - a11) c in1 - 10 pf input capacitance (/w) c in2 - 14 pf input capacitance (/ras0, /ras1) c in3 - 14 pf input capacitance (/cas0 - /cas3) c in4 - 14 pf input/output capacitance (dq0 - 31) c dq1 - 14 pf ac characteristics ( 0 o c t a 70 o c , vcc = 3.3v 10%, see notes 1,2.) - 5 - 6 standard operation symbol min max min max unit random read or write cycle time t rc 84 104 ns access time from /ras t rac 50 60 ns access time from /cas t cac 13 15 ns access time from column address t aa 25 30 ns /cas to output in low - z t clz 3 3 ns transition time (rise and fall) t t 1 50 1 50 ns /ras precharge time t rp 30 40 ns /ras pulse width t ras 50 10k 60 10k ns /ras hold time t rsh 13 15 ns /cas hold time t csh 38 45 ns /cas pulse width t cas 8 10k 10 10k ns /ras to /cas delay time t rcd 20 37 20 45 ns /ras to column address delay time t rad 15 25 15 30 ns /cas to /ras precharge time t crp 5 5 ns row address set - up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set - up time t asc 0 0 ns
hanbit hm d4m32m2ve url:www.hbe.co.kr h anbit electronics co.,ltd. rev.1.0 (august.2002) 5 column address hold time t cah 8 10 ns column address to /ras lead time t ral 25 30 ns read command set - up time t rcs 0 0 ns read command hold referenced to /cas t rch 0 0 ns read command hold referenced to /ras t rrh 0 0 ns write command hold time t wch 10 10 ns write command pulse width t wp 10 10 ns write command to /ras lead time t rwl 10 10 ns write command to /cas lead time t cwl 8 10 ns data - in set - up ti me t ds 0 0 ns data - in hold time t dh 8 10 ns refresh period t ref 64 64 ns write command set - up time t wcs 0 0 ns /cas setup time (c - b - r refresh) t csr 5 5 ns /cas hold time (c - b - r refresh) t chr 10 10 ns /ras precharge to /cas hold time t rpc 5 5 ns access time from /cas precharge t cpa 35 40 ns fast page mode cycle time t pc 28 35 ns /cas precharge time (fast page) t cp 8 10 ns /ras pulse width (fast page ) t rasp 50 100k 60 100k ns /w to /ras precharge time (c - b - r refresh) t wrp 10 10 ns /w to /ras hold time (c - b - r refresh) t wrh 10 10 ns notes 1. an initial pause of 200 m s is required after power - up followed by any 8 /ras - only or /cas - before - /ras refresh cycles before proper device operation is achieved. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih(min) and v il(max) and are assumed to be 5ns for all inputs. 3. measured with a load equivalent to 1ttl loads and 100pf 4. operation within the t rcd(max) limit insur es that t rac(max) can be met. t rcd(max) is specified as a reference point only. if t rcd is greater than the specified t rcd(max) limit, then access time is controlled exclusively by t cac . 5. assumes that t rcd 3 t rcd(max) 6. t ar , t wcr , t dhr are referenced to t r ad(max) 7.this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 8. t wcs , t rwd , t cwd and t awd are non restrictive operating parameter. they are included in the data sheet as electr ical characteristic only. if t wcs 3 twcs(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. either t rch or t rrh must be satisfied for a read cycle. 10. these parameters are referenc ed to the /cas leading edge in early write cycles and to the /w leading edge in read - write cycles. 11. operation within the t rad(max) limit insures that t rac(max) can be met. t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit. then access time is controlled by t aa .
hanbit hm d4m32m2ve url:www.hbe.co.kr h anbit electronics co.,ltd. rev.1.0 (august.2002) 6 timing diagram please refer to attached timing diagram chart (i) packaging informatio n simm design o r dering inf ormation part number density org. package refresh cycle vcc speed HMD4M32M2VEg - 5 16mbyte 4mx 32bit 72 pin - simm 4,096 cycles 64ms ref. 3.3v 50ns HMD4M32M2VEg - 6 16mbyte 4mx 32bit 72 pin - simm 4,096 cycles 64ms ref. 3.3v 60ns 10.16 mm 107.95 mm 95.25 mm 6.35 mm r1.57 1.0 mm 6.35 2.0 0 1 9 . 00 6.35 mm 101.19 mm r1.57 mm 3.18 0.51 3.38 mm max 5.08 1.2 7 0.08 mm 0.25 mm max min 2.54 mm 1.27 gold : 1.04 10 mm
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